Solid-state camera including a charge coupled device

ABSTRACT

To provide a solid-state image sensor, wherein no field adjustment of timing pulse phases used in the signal processor or of signal balances is needed, and noise performance is more improved, with a simple, miniaturized and economical configuration, a solid-state image sensor ( 1 ) of the invention comprises: a CCD ( 2 ) configured on a semiconductor chip for generating a CCD signal according to an optical image focused on a sensor area thereof; an on-chip signal processor ( 4 ) configured on the semiconductor chip by way of the same fabrication process with the CCD including a noise reduction circuit for eliminating noises from the CCD signal, an AGC circuit for amplifying output of of the noise reduction circuit; and a timing pulse generator ( 3 ) configured on the semiconductor chip by way of the same fabrication process with the CCD ( 2 ) for generating timing pulses used the on-chip signal processor. The on-chip signal processor ( 4 ) of the solid-state image sensor ( 1 ) may further comprise an A/D converter for converting output of the AGC circuit into a digital signal.

BACKGROUND OF THE INVENTION

The present invention relates to a solid-state image sensor.

FIG. 8 is a block diagram illustrating a conventional solid-statecamera, wherein a charge coupled device (hereafter abbreviated as CCD)is applied, comprising a CCD 91, a signal processor 97, a videoprocessor 98, a CCD driver 92 and a timing signal generator 93.

FIG. 9 is a schematic diagram illustrating a configuration of the CCD91, wherein an object image is focused on a sensor area (photoelectrictransducer section) 100, and converted into electric chargescorresponding to intensity of incident light by photo-diodes 101.Generated electric charges are transferred to vertical CCDs 102 throughreading transfer gates. The vertical CCDs 102 are driven by verticaltransfer pulses φV1 to φV4 and transfer the electric charges horizontalCCD 103 in order. The horizontal CCD 103 is driven by horizontaltransfer pulses φH1 and φH2 and transfers the electric charges to anoutput amplifier 104 to be output outside, namely, to the signalprocessor 97 of FIG. 8. To the output amplifier 104, a reset pulse φR issupplied for resetting the output amplifier 104 from remaining chargefor every pixel (photo-diode).

The signal processor 97 comprises, in general, a noise reduction circuit94, an AGC (Auto Gain Control) circuit 95 and an A/D (Analog to Digital)converter 96.

The noise reduction circuit 94 takes charge of removing amplifier noisesand reset noises among noises included iii the output signal of the CCD91, that is, amplifier noises, shot noises and reset noises. The AGCcircuit 95 amplifies and maintains signal level of the output of thenoise reduction circuit 94 to a fixed level. Output of the AGC circuit95 is converted into a digital signal of a certain bit width by the A/Dconverter 96 to be processed by the video processor 98. In theconventional CCD camera of FIG. 8, the video signal is output afterconverted into digital signal. However, analog signal may be outputdirectly.

In the video processor 98, low-pass filtering, γ-correction, peakclipping, amplification and so on of the output of the signal processor97 are performed for outputting a video signal to be represented on adisplay device.

Driving pulses φH, φR, and φV for driving the CCD 91 are supplied fromthe CCD driver 92. The timing signal generator 93 generates timingsignals such as a CCD driving pulse signal, a clock signal, or asample-hold pulse signal to be delivered to each of the above parts.

The above described parts, that is, the signal processor 97, the videoprocessor 98, the CCD driver 92 and the timing signal generator 93 areheretofore provided outside the CCD 91. However, personal video moviesor digital cameras are widely spread recently, and more compact andeconomical equipment has become earnestly desired. For the purpose,circuit scale reduction and device miniaturization are actively pursuednow.

As a prior art of the circuit scale reduction and the deviceminiaturization, configuration of the signal processor on the samesemiconductor chip with the CCD is proposed in a Japanese patentapplication laid open as a Provisional Publication No. 259668/'89 inorder to reduce the circuit scale and the cost as well of thesolid-state camera.

FIG. 10 is a block diagram illustrating a solid-state camera of theprior art having a CCD 111 wherein a signal processor (frequencydivider) 112 is included, and its peripheral circuits consisting of avertical driver 113, horizontal driver 114, a generator of clock pulsesand synchronous signals (hereafter abbreviated as SSCG) 117, asub-carrier generator 118 and a video processor 119.

The solid-state camera of FIG. 10 operates as follows.

A clock pulse generator section (abbreviated as CG) 115 of the SSCG 117generates CCD driving pulses (φV, φH and φR) to be supplied to thevertical driver 113 and the horizontal driver 114. The vertical driver113 and the horizontal driver 114 supply the CCD driving pulses aftervoltage-amplified. The frequency divider 112 configured on the CCD 111generates a horizontal synchronous signal HD according to a reset pulseφR of the CCD driving pulses, which is returned to a synchronous signalgenerator section (abbreviated as SSG) 116 of the SSCG 117. Thesub-carrier generator 118 generates at color sub-carrier signal Fsc tobe supplied to the video processor 119. The video processor 119generates a video signal to be output from output of the CCD 111 byperforming necessary processing ill the same way with the videoprocessor 98 of FIG. 8.

As above described, a noise reduction is intended in the prior art byproviding the frequency divider 112 separately from the SSCG 117 inorder to prevent the CCD driving pulses to be affected from noisesderived from the frequency divider 112, and a miniaturization of theequipment is realized as well by configuring the frequency divider 112on the CCD 111.

Another prior art is disclosed in a Japanese patent application laidopen as a Provisional Publication No. 184978/'86 and that of ProvisionalPublication No. 186080, wherein the A/D converter is configured on theCCD for the equipment miniaturization and the cost reduction.

FIG. 11 is a circuit configuration illustrating the A/D converterdesigned on the CCD described in the Provisional Publication No.186080/'87.

Referring to FIG. 11, numerals 121 and 122 denote transfer electrodes ofa charge coupled device each driven with each of transfer pulses φ1 andφ2. Between each pair of the transfer electrodes 121 and 122, floatingelectrodes 123 to 125 are inserted. The charge coupled device, a drainelectrode 126 being provided for absorbing signal electrons at an endthereof, operates as a tapped delay line 127 halving tap electrodescharge-coupled therewith. Therefore, signal electrons transferred fromthe other end in a direction indicated by an allow 128 are transferredin the delay line 127 in order, and at the same time, they are detectednondestructively by the floating electrodes 123 to 125 each connected toan input terminal of each of analog comparators 129 to 131.

To another input terminal of each of the analog comparators 129 to 131,each of reference voltages obtained by dividing a main reference voltagewith resisters 132 to 135 of the same resistance is supplied. That is,when potential of the maim reference voltage supplied to a terminal 136is VR, potentials 3VR/4, VR/2 and VR/4 are impressed to the analogcomparators 129 to 131, respectively.

Representing signal potential detected by the floating electrode 123 byVS, output C1 of the analog comparator 129 becomes at logic ‘1’ (highlevel) when VS>3VR/4, and otherwise at logic ‘0’ (low level). Otheranalog comparators 130 and 131 operate in the same way except fordifference of the reference voltage VR/2 or VR/4. Therefore, logicaloutputs C1 to C3 of the analog comparators 129 to 131 are obtained asrepresented by following Table 1 according to value of the signalpotential VS.

TABLE 1 Comparative Output Encoder Output Condition C1 C2 C3 D1 D2  VS > 3VR/4 1 1 1 1 1 3VR/4 > VS > VR/2 0 1 1 1 0  VR/2 > VS > VR/4 0 01 0 1  VR/4 > VS 0 0 0 0 0

That is, the outputs C1, C2 and C3 become all at logic ‘1’ whenVS>3VR/4, the outputs C2 and C3 being at logic ‘1’ when 3VR/4>VS>VR/2,only the output C3 at logic ‘1’ when VR/2>VS>VR/4 and none at logic ‘1’when VR/4>VS.

Each of the digital outputs C1 to C3 is then delayed through each ofdigital shifts registers 137 to 139 corresponding to detection timing ofthe same signal electrons of the floating electrode 123 to 125 delayedin the order by a clock cycle. By delaying each of the digital outputsC1, C2 and C3 for 3, 2 and 1 clock cycles by the digital shift registersdriven by the same clock signal with that driving the delay line 127,the transfer delays are compensated. Thus, the digital outputs C1 to C3of the same signal electrons are input to an encoder 140 ranged at thesame timing, and converted into a binary code of two bits D1 and D2, aslisted in Table 1.

Besides these prior arts, some examples are disclosed also in Japanesepatent applications laid open as Provisional Publications No. 32776/'96and No. 154980/'87. In the former document, a RAM (Read Only Memory) isconfigured on a CCD together with an A/D converter, and aln A/Dconverter is provided on the same semiconductor chip with a MOS typeimage sensor in the latter document.

However, there are following problems in these prior arts.

The first problem is that only a part of peripheral circuits isconfigured on the same semiconductor chip of the solid-state imagesensor in every of the prior arts. Therefore, field adjustment of timingpulse phases or signal balance with external circuits outside thesemiconductor chip has been inevitable for eliminating pulse delaydifferences, dulling of wave forms or ringing interferences caused byperformance dispersion of active or passive elements of the externalcircuits or by wiring arrangement connecting them.

The second problem is that the miniaturization effect of the equipmentis limited even when a part of peripheral circuits is configuredon-chip. For replying to severe market requirement for theminiaturization, main part of the peripheral circuits should beconfigured together with the solid-state image sensor.

The third problem is that noises are susceptible to be mingled in theoutput signal of the CCD, even when the frequency divider is configuredon the solid-state image sensor chip as described in the aboveProvisional Publication No. 259668/'89. The reason is that a long wiringis left needed for the high-impedance output signal of the CCD which issupplied to external circuit directly without signal processing. Thismakes noise performance easily dependent of length or path of wirings orarrangement of equipment parts.

SUMMARY OF THE INVENTION

Therefore, a primary object of the present invention is to provide asolid-state image sensor wherein is needed to field adjustment of timingpulse phases used in the signal processor or of signal balances. Anotherobject of the invention is to provide a solid-state image sensor havingnoise performance more improved with a simple, miniaturized andeconomical configuration.

In order to achieve the objects, a solid-state image sensor of theinvention comprises:

a CCD configured on a semiconductor chip for generating a CCD signalaccording to an optical image focused on a sensor area thereof;

an on-chip signal processor configured on the semiconductor chip by wayof the same fabrication process with the CCD including a noise reductioncircuit for eliminating noises from the CCD signal, and an AGC circuitfor amplifying output of the noise reduction circuit; and

a timing pulse generator configured on the semiconductor chip by way ofthe same fabrication process with the CCD for generating timing pulsesused by the on-chip signal processor.

Therefore, uniformity of circuit elements can be easily attained, fieldadjustment of phases of timing pulses being made unnecessary, as well asrealization of further miniaturization of the equipment. The noiseperformance is also improved, since wiring paths connecting circuitelements in the timing pulse generator and the on-chip signal processorcan be shortened.

The on-chip signal processor may further comprise an A/D converter forconverting output of the AGC circuit into a digital signal for enablinga user to select either of analog output or digital output.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing, further objects, features, mid advantages of thisinvention will become apparent from a consideration of the followingdescription, the appended claims, and the accompanying drawings whereinthe same numerals indicate the same or the corresponding parts.

In the drawings:

FIG. 1 is a block diagram illustrating a configuration of an embodimentof the invention;

FIG. 2 is a schematic diagram illustrating the CCD 2 of FIG. 1;

FIG. 3 is a block diagram illustrating detail of the on-chip signalprocessor of FIG. 1;

FIG. 4 is a circuit diagram illustrating configuration of the CDScircuit applied to the noise reduction circuit 32 of FIG. 3;

FIG. 5 is a timing chart illustrating operation of the CDS circuit ofFIG. 4;

FIG. 6 is a block diagram illustrating configuration of the AGC circuit33 of FIG. 3;

FIG. 7 is a block diagram illustrating another configuration of the AGCcircuit 33 of FIG. 3;

FIG. 8 is a block diagram illustrating a conventional solid-statecamera;

FIG. 9 is a schematic diagram illustrating a configuration of the CCD 91of FIG. 8;

FIG. 10 is a block diagrams illustrating a solid-state camera of anotherprior art; and

FIG. 11 is a circuit configuration illustrating the A/D converterdesigned on the CCD according to still another prior art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Now, embodiments of the present invention will be described inconnection with the drawings.

FIG. 1 is a block diagram illustrating a configuration of an embodimentof the invention.

Referring to FIG. 1, a solid-state image sensor 1 according to theembodiment is configured on a semiconductor chip and comprises a CCD 2,a timing pulse generator (hereafter abbreviated as TG) 3 and an on-chipsignal processor 4 including a noise reduction circuit, an auto gaincontrol circuit (AGC) and an A/D converter.

Outside the solid-state image sensor 1, a CCD driver 5, a synchronoussignal generator (hereafter abbreviated as SYNC) 6, and a gaincontroller 7 are provided.

CCD driving pulses (φV, φH and φR) are generated by the SYNC 6 andsupplied to the CCD driver 5 to be voltage-amplified for driving the CCD2 on the solid-state image sensor 1. Output signal of the CCD 2 istransferred to the on-chip signal processor 4, whereby processings ofnoise reduction, AGC and A/D conversion are performed to be output as adigital output signal as well as an analog output signal.

One of the CCD driving pulses supplied to the CCD 2, a horizontaldriving pulse φH, for example, is delivered to the TG 3 as a clocksignal CLK. By counting pulses of the clock signal CLK, that is, thehorizontal driving pulse φH in the embodiment, the TG 3 generatesvarious timing pulses used in the following on-chip signal processor 4.

Now, operation of the CCD 2 of FIG. 1 is described referring to aschematic diagram of FIG. 2.

An object image is focused on a sensor area (photoelectric transducersection) 20 of the CCD 2, and converted into electric chargescorresponding to intensity of incident light by photo-diodes 21.Generated electric charges are transferred to vertical CCDs 22 throughreading transfer gates. The vertical CCDs 22 are driven by verticaltransfer pulses φV1 to φ4 and transfer the electric charges to ahorizontal CCD 23 in order. The horizontal CCD 23 is driven byhorizontal transfer pulses φH1 and φH2 and transfers the electriccharges to an output amplifier 24 to be output. A reset pulse φR issupplied for resetting the output amplifier 104 from remaining chargefor every pixel (photo-diode).

CCD signal output from the output amplifier 24 is transferred to thefollowing on-chip signal processor 4.

FIG. 3 is a block diagram illustrating detail of the on-chip signalprocessor 4, comprising a noise reduction circuit 32, an AGC circuit 33and an A/D converter circuit 34.

The noise reduction circuit 32 takes charge of removing amplifier noisesand reset noises among noises included in the output signal of the CCD2, that is, amplifier noises, shot noises and reset noises. To the noisereduction circuit 32, a CDS (Correlated Double Sampling) circuit isapplied, for example. The AGC circuit 33 amplifies and maintains signallevel of the output of the noise reduction circuit 32 to a fixed level.Output of the AGC circuit 33 is converted into a digital signal of acertain bit width, 8 bits, for example, by the A/D converter 34.

Now, concrete examples of circuit elements of the on-chip signalprocessor 4 will be described.

The noise reduction circuit 32 can be realized by way of the CDS circuithaving at circuit configurational illustrated in FIG. 4, for example,comprising;

a first buffer 41 for buffering the CCD output 51 with a low impedance,

a clamp condenser 42 for charging output of the first buffer 41 into afirst electrode thereof,

a transistor 43 for clamping potential of a second electrode of theclamp condenser 42 at a clamp level Vcl when it is made ON gated by aclamp pulse 52,

a second buffer 45 for buffering potential of the second electrode ofthe clamp condenser 42 with a low impedance,

a sampling transistor 46 for sampling output of the second buffer 45when it is made ON gated by all S/H (Sample/Hold) pulse 53, and

a hold condenser 47 for holding output of the second buffer 45 sampledby the sampling transistor 46.

FIG. 5 is a timing chart illustrating operation of the CDS circuit ofFIG. 4. In each cycle of the CCD output 51 corresponding to each pixel,the signal level is once maintained at a feed-through level 55 after areset impulse 54 derived by the reset pulse φR, which is followed by asignal level 56 with a potential difference Vs representing each pixelcharge. First, according to the clamp pulses 52 becoming at HIGH levelat timings shown in FIG. 5, the clamp transistor 43 of FIG. 4 is turnedto ON and clamps the feed-through level at a fixed DC level of the clamplevel Vcl. Then input, and consequently, output of the second buffer 45falls down by a signal level Vs from the clamp level, which is sampledby the sample transistor 46 turned to ON gated by the S/H pulse becomingat HIGH level at timings shown in FIG. 5, and charged into the holdcondenser 47 to be output.

Thus, the reset noise and the amplifier noise component included in thefeed-through level 55 and the signal level 56 are both eliminated andcancelled from the CCD output 51.

FIG. 6 is a block diagram illustrating configuration of the AGC circuit33 comprising;

a variable gain amplifier 61 for amplifying input signal to a fixedlevel,

a level detector 62 which detects mean level of the output signalamplified by the variable gain amplifier 61 by integrating the signallevel for a certain period, for example,

a comparator 63 whereof an input terminal is supplied with output of thelevel detector 62, and

a switch 64 connected to another input terminal of the comparator 63 forselecting either of a prefixed reference voltage Vref1 or at variablereference voltage Vref2 supplied from the gain controller 7.

The comparator 63 outputs ant AGC control signal for controlling thevariable amplifier 61 so that the output of the level detector 62coincide to the prefixed reference voltage Vref1 or the variablereference voltage Vref2, by comparing them. Thus, the output signallevel of the variable amplifier 61 is controlled to maintain a fixedlevel by way of a feedback loop consisting of the variable amplifier 61,the level detector 62 and the comparator 63.

In the above example, the external reference voltage Vref2 is describedto be supplied from an analog gain controller circuit. However, it maybe controlled with a digital signal by further providing a D/A (Digitalto Analog) converter 71 as illustrated in FIG. 7. As to the D/Aconverter 71, any appropriate con-conventional D/A converter can beapplied.

Returning to FIG. 3, output of the AGC circuit 33 thus obtained isoutput directly as an analog output signal, and at the same time,supplied to the A/D converter 34 to be converted into a digital outputsignal. As to also the A/D converter 34 of FIG. 3, any appropriateconventional A/D converter can be applied.

Thus, the analog output signal and the digital output signal of thesolid-state image sensor 1 of the embodiment are obtained, so thateither thereof may be used according to circuit configuration of videoprocessor wherein low-pass filtering, γ-correction, peak clipping,amplification and so on are to be performed. However, the A/D converter34 may be avoided when the digital output is not necessary.

The TG 3 and the on-chip signal processor 4 can be configured on thesame semiconductor chip by way of the same MOS fabrication process atthe same time with the CCD 2.

As heretofore described, the solid-state image sensor 1 of the inventionhas following merits.

1. Field adjustment of phases of timing pulses is made unnecessary,since uniformity of circuit elements can be easily attained byconfiguring the timing pulse generator 3 and the on-chip signalprocessor 4 on the same semiconductor chip by way of the same MOSfabrication process with the CCD 2.

2. Further miniaturization of the equipment can be realized, since thetiming pulse generator 3 and the signal processor 4 including allnecessary circuit elements except for the CCD driver circuit 5 and theSYNC 6 are configured on the solid-state image sensor 1.

3. The noise performance is improved, since wiring paths connectingcircuit elements in the timing pulse generator 3 and the on-chip signalprocessor 4 can be shortened.

4. Clock noises because of interference from high-frequency clock signalare reduced, since the timing pulse generator 3 is clocked directly witha driving pulse of the CCD 2, avoiding additional wiring for supplying aclock signal to the timing pulse generator 3 from outside.

5. Output signal level can be controlled optionally from outside, sincereference voltage of the AGC circuit 33 can be controlled by an analogor digital external signal.

1. A solid-state image sensor comprising: a CCD (Charge Coupled Device)having a horizontal CCD and a vertical CCD configured on a singlesemiconductor chip for generating a CCD signal according to an opticalimage focused on a sensor area thereof; an on-chip signal processorconfigured on the semiconductor chip by way of the same fabricationprocess with the CCD including at least a noise reduction circuit foreliminating noise from the CCD signal and an AGC (Automatic GainControl) circuit for amplifying output of the noise reduction circuit;and a timing pulse generator configured on the semiconductor chip by wayof the same fabrication process with the CCD for generating timingpulses used by the on-chip signal processor.
 2. The solid-state imagesensor recited in claim 1, said on-chip signal processor furthercomprising an A/D (Analog to Digital) converter for converting output ofthe AGC circuit into a digital signal.
 3. The solid-state image sensorrecited in claim 1, wherein one of CCD driving pulses supplied from anexternal circuit for driving the CCD is directly supplied to the timingpulse generator as a clock signal used in the timing pulse generator. 4.The solid-state image sensor recited in claim 1, wherein gain of the AGCcircuit is designed to be controlled by an analog signal delivered froman external circuit.
 5. The solid-state image sensor recited in claim 1,wherein gain of the AGC circuit is designed to be controlled by adigital signal delivered from an external circuit.
 6. The solid-stateimage sensor recited in claim 2, wherein either of output of the AGCcircuit or output of the A/D converter is selected to be used.
 7. Asolid-state image sensor comprising: CCD (Charge Coupled Device) havinga horizontal CCD and a vertical CCD configured on a single semiconductorchip for generating a CCD signal according to an optical image focusedon a sensor area thereof; an on-chip signal processor configured on thesemiconductor chip by way of a same MOS fabrication process with the CCDincluding at least a noise reduction circuit for amplifying output ofthe noise reduction circuit; and a timing pulse generator configured onthe semiconductor chip by way of the same fabrication process with theCCD for generating timing pulses used by the on-chip signal processor.8. The solid-state image sensor recited in claim 7, said on-chip signalprocessor further comprising an A/D (Analog to Digital) converter forconverting output of the AGC circuit into a digital signal.
 9. Thesolid-state image sensor recited in claim 7, wherein one of CCD drivingpulses supplied from an external circuit for driving the CCD is directlysupplied to the timing pulse generator as a clock signal used in thetiming pulse generator.
 10. The solid-state image sensor recited inclaim 7, wherein gain of the AGC circuit is designed to be controlled byan analog signal delivered from an external circuit.
 11. The solid-stateimage sensor recited in claim 7, wherein gain of the AGC circuit isdesigned to be controlled by a digital signal delivered from an externalcircuit.
 12. The solid-state image sensor recited in claim 8, whereineither of output of the AGC circuit or output of the A/D converter isselected to be used.